TEWKSBURY, MA., December 6, 2022 – Avery Design Systems Inc., an innovator in functional IC verification productivity solutions, today announced the availability of a major new release to its patented SimXACT™ analysis solutions, adding features for sequential false X analysis and automatic repair and improved analysis and debug of clock gating logic. The new release also improves overall runtime performance.
SimXACT automates the tedious process of analyzing X propagations in gate-level simulations due to RTL vs. gate-level mismatches. These issues typically arise from gate-level simulator X-pessimism handling in glue logic and gated clocking and overly pessimistic library cell modelling.
SimXACT’s hydrid formal analysis runs during normal logic simulation, proving and fixing on-the-fly any false X’s arising from the simulated X pessimism present on flops, latches, memory inputs, and output pads.
The new SimXACT-SA analyzes X propagations through multi-level sequential re-convergent logic and resolves false X’s so they do not propagate and cause gate-level simulation mismatch compared to RTL simulation. Sequential analysis used to be only suited to conventional formal property checking solutions. Now SimXACT-SA’s hybrid formal analysis enables the use of simulation case-driven stimulus for more precise handling of sequential X propagation scenarios.
Highlights of the SimXACT and SimXACT-SA include:
· New sequential analysis engine that tracks X logic over multiple cycles and resolving sequential false Xs when detected
· New patented technology that identifies and fixes false Xs created by nested clock gaters where conflicting clock gater enable conditions can create false Xs on the downstream FFs
· New GLS clock debug tool for comparing islands of FFs controlled by the same clock gaters between 0-delay and SDF-annotated simulations to help root cause hard-to-debug test failures
· New algorithm and heuristics for SimXACT formal engine that better predict functional impact of false Xs, resulting in smaller numbers of generated fixes while maintaining effectiveness for resolving false Xs that are functionally relevant
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Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.